Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide control systems and methods for reliable over-current protection. Merely by way of example, some embodiments of the invention have been applied to power converters. But it would be recognized that the invention has a much broader range of applicability.
Power converters are widely used for consumer electronics such as portable devices. The power converters can convert electric power from one form to another form. As an example, the electric power is transformed from alternate current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. Additionally, the power converters can convert the electric power from one voltage level to another voltage level.
The power converters include linear converters and switch-mode converters. The switch-mode converters often use pulse-width-modulated (PWM) or pulse-frequency-modulated mechanisms. These mechanisms are usually implemented with a switch-mode controller including various protection components. These components can provide over-voltage protection, over-temperature protection, over-current protection (OCP), and over-power protection (OPP). These protections can often prevent the power converters and connected circuitries from suffering permanent damage.
For example, a power converter includes a switch and transformer winding that is in series with the switch. The current flowing through the switch and transformer winding may be limited by an OCP system. If the OCP system is not effective, the current can reach a level at which damage to the switch is imminent due to excessive current and voltage stress at switching or thermal run-away during operation. For example, this current level can be reached when the output short circuit or over loading occurs. Consequently, the rectifier components on the transformer secondary side are subject to permanent damage due to excessive voltage and current stress in many offline flyback converters. Hence an effective OCP system is important for a reliable switch-mode converter.
FIG. 1 is a simplified conventional switch-mode converter with over-current protection. A switch-mode converter 100 includes an OCP comparator 110, a PWM controller component 120, a gate driver 130, a switch 140, resistors 150, 152, 154, and 156, and a primary winding 160. The OCP comparator 110, the PWM controller component 120, and the gate driver 130 are parts of a chip 180 for PWM control.
For example, the PWM controller component 120 generates a PWM signal 122, which is received by the gate driver 130. In yet another example, the OCP comparator 110 receives and compares an over-current threshold signal 112 (e.g., Vth_oc) and a current sensing signal 114 (e.g., VCS), and sends an over-current control signal 116 to the PWM controller component 120. When the current of the primary winding is greater than a limiting level, the PWM controller component 120 turns off the switch 140 and shuts down the switch-mode power converter 100.
For switch-mode converter, a cycle-by-cycle or pulse-by-pulse control mechanism is often used for OCP. For example, the cycle-by-cycle control scheme limits the maximum current and thus the maximum power delivered by the switch-mode converter. This limitation on maximum power can protect the power converter from thermal run-away. Some conventional OCP systems use an adjustable OCP threshold value based on line input voltage, but the actual limitation on maximum current and thus maximum power is not always constant over a wide range of line input voltage. Other conventional OCP systems use additional resistors 152 and 154 that are external to the chip 180 and inserted between Vin and the resistor 150 as shown in FIG. 1. But the resistor 152 consumes significant power, which often is undesirable for meeting stringent requirements on low standby power. For example, the resistor 152 of 2 MΩ can dissipate about 70 mW with input AC voltage of 264 volts.
As shown in FIG. 1, the current limit is expressed as follows:
                              I          Limit                =                                                            V                in                                            L                p                                      ⨯                          t              on                                =                                    V              th_oc                                      R              s                                                          (                  Equation          ⁢                                          ⁢          1                )            where ILimit represents the current limit. For example, the current limit is the current threshold for triggering over-current protection. Additionally, Vin is a bulk voltage (e.g., associated with the line input voltage VAC) at node 190, and Vth_oc is the voltage level at an input terminal 112 of the OCP comparator 110. Rs is the resistance of the resistor 150, and Lp is the inductance of the primary winding 160. Moreover, ton represents on time of the switch 140 for each cycle. Accordingly, the maximum energy ε stored in the primary winding 160 isε=1/2×Lp×ILimit2=PT  (Equation 2)where T represents the clock period, and P represents the maximum power. So the maximum power P can be expressed as follows:
                    P        =                                                            L                p                            ×                              I                Limit                2                                                    2              ⁢              T                                =                                                    V                                  i                  ⁢                                                                          ⁢                  n                                2                            ×                              t                on                2                                                    2              ×                              L                p                            ×              T                                                          (                  Equation          ⁢                                          ⁢          3                )            
Therefore the power can be limited by controlling the current limit ILimit. But Equation 3 does not take into account the “delay to output” that includes the propagation delay through a current sense path to the switch 140. For example, the propagation delay includes propagation delays through the OCP comparator 110, the PWM controller component 120, the gate driver 130, and the response delay of turning off of the switch 140. During the “delay to output,” the switch 140 remains on, and the input current through the switch 140 keeps ramping up despite the current has already reached the threshold level of the OCP comparator 110. The extra current ramping amplitude, ΔI, due to the “delay to output” is proportional to the bulk voltage Vin as follows:
                              Δ          ⁢                                          ⁢          I                =                                            V                              i                ⁢                                                                  ⁢                n                                                    L              p                                ×                      T            delay                                              (                  Equation          ⁢                                          ⁢          4                )            where Tdelay represents the “delay to output.”
FIG. 2 is a simplified diagram showing conventional relationship between extra current ramping amplitude and bulk voltage. As shown in FIG. 2, the actual maximum current IPEAK1 that corresponds to higher Vin is larger than the actual maximum current IPEAK2 that corresponds to lower Vin. Accordingly, the actual maximum power is not constant over a wide range of bulk voltage. Hence the actual maximum power is expressed as follows:
                    P        =                                                            L                p                            ×                                                (                                                            I                      Limit                                        +                                          Δ                      ⁢                                                                                          ⁢                      I                                                        )                                2                                                    2              ⁢              T                                =                                                    V                                  i                  ⁢                                                                          ⁢                  n                                2                            ×                                                (                                                            t                      on                                        +                                          T                      delay                                                        )                                2                                                    2              ×                              L                p                            ×              T                                                          (                  Equation          ⁢                                          ⁢          5                )            
For example, Tdelay depends on internal delays, gate charges, and circuitry related to the gate driver 130. In another example, for the predetermined switch-mode converter 100, Tdelay is constant, and hence the actual maximum power depends on the bulk voltage. To compensate for variations of the actual maximum power, the threshold for over-current protection should be adjusted based on the bulk voltage.
FIG. 3 is a simplified diagram showing conventional relationship between current threshold and bulk voltage. The bulk voltage Vin2 is lower than the bulk voltage Vin1, and the current threshold Ith_oc_vin2 for Vin2 is larger than Ith_oc_vin1 for Vin1 as shown in FIG. 3. The current threshold decreases with increasing bulk voltage Vin. At the current threshold, the over-current protection is triggered. The resulting maximum current IPEAK1 for higher Vin is the same as the resulting maximum current IPEAK2 for lower Vin.
For example, the current threshold has the following relationship with the bulk voltage:
                              I          th_oc                ≈                                            I              th_oc                        ⁡                          (                              V                                  i                  ⁢                                                                          ⁢                  n                  ⁢                                                                          ⁢                  1                                            )                                -                                                                      V                                      i                    ⁢                                                                                  ⁢                    n                                                  -                                  V                                      i                    ⁢                                                                                  ⁢                    n                    ⁢                                                                                  ⁢                    1                                                                              L                p                                      ⁢                          T              delay                                                          (                  Equation          ⁢                                          ⁢          6                )            where Ith_oc is the current threshold, Vin is the bulk voltage, Lp is the inductance of the primary winding, and Tdelay is the “delay to output.” Additionally, Ith_oc(Vin1) is the current threshold that is predetermined for the bulk voltage Vin1. For example, Vin1 is the minimum bulk voltage. In another example, the current is sensed that flows through the switch and the primary winding. If the sensed current reaches Ith_oc, the PWM controller component sends a signal to turn off the switch. After “delay to output,” the switch is turned off.
In Equation 6, the second term
                    V                  i          ⁢                                          ⁢          n                    -              V                  i          ⁢                                          ⁢          n          ⁢                                          ⁢          1                            L      p        ⁢      T    delay  represents a threshold offset to compensate for the effects of “delay to output.” FIG. 4 is a simplified diagram showing conventional relationship between threshold offset and bulk voltage. As shown in FIG. 4, the term
      T    delay        L    p  is the slope that depends on the “delay to output” and the inductance of primary winding. As shown in FIG. 4, the current threshold decreases with increasing bulk voltage.
There are at least two conventional approaches to implement the current threshold as a function of bulk voltage according to FIG. 4. In one example, the bulk voltage is sensed to generate an offset DC voltage proportional to bulk voltage in order to compensate for the effects of “delay to output” as shown in Equation 6.
In another example, the bulk voltage is sensed based on the maximum width of the PWM signal. The PWM signal is applied to the gate of a switch in series to the primary winding of a power converter. FIG. 5 is a simplified diagram showing conventional relationship between PWM signal maximum width and bulk voltage. As shown in FIG. 5, the maximum current is constant with respect to bulk voltage, and the maximum width of PWM signal varies with bulk voltage. The maximum current IPEAK1 equals the maximum current IPEAK2. The maximum current IPEAK1 corresponds to a higher bulk voltage and a PWM signal 510, and the maximum current IPEAK2 corresponds to a lower bulk voltage and a PWM signal 520. As shown in FIG. 5, the maximum width for the PWM signal 510 is narrower for higher bulk voltage, and the maximum width for the PWM signal 520 is wider for lower bulk voltage. The bulk voltage is represented by the maximum width of the PWM signal if the maximum current is constant with respect to bulk voltage. Accordingly, the maximum width of the PWM signal can be used to determine the threshold offset to compensate for the effects of “delay to output” as shown in Equation 6.
According to FIG. 5, the compensation can be realized by generating a current threshold, Ith_oc, which is a function of the maximum width of the PWM signal. For example, the current threshold is equal to Ith_oc_1 for the PWM signal 510 and Ith_oc_2 for the PWM signal 520. In another example, the slope of Ith_oc with respect to the maximum width is properly chosen to compensate for the effects of “delay to output” as shown in Equation 6. The selected slope takes into account information about power converter components that are external to the chip for PWM control. The external components may include the primary winding, a current sensing resistor and a power MOSFET.
Additionally, to achieve high efficiency, a power converter usually works in CCM mode at low bulk voltage and works in DCM mode at high bulk voltage. FIG. 6 shows simplified conventional current profiles for primary winding in CCM mode and DCM mode. The current profiles describe current magnitudes as functions of time. As shown in FIG. 6(a), the current for primary winding increases from I_L to a current limit I_p within a pulse width at each cycle in DCM mode. For example, I_L is equal to zero. The energy delivered to the load at each cycle isε=1/2×Lp×(I_p1)2  (Equation 7)
In contrast, as shown in FIG. 6(b), the current for primary winding increases from I_i2 to a current limit I_p2 within a pulse width at each cycle in CCM mode. For example, I_i2 is larger than zero. The energy delivered to the load at each cycle isε=1/2×Lp×[(I_p2)2−(I_i2)2]  (Equation 8)where the ratio of
  I_i2  I_p2can vary with bulk voltage. For example, the ratio increases with decreasing bulk voltage. As described in Equations 7 and 8, if the two current limits I_p1 and I_p2 are equal, the amount of energy delivered to the load in DCM mode is higher than the amount of energy delivered to the load in CCM mode at each cycle.
FIG. 7 shows a simplified diagram for maximum energy delivered to load at each cycle as a conventional function of bulk voltage. As a function of bulk voltage, the current limit, which equals either I_p1 or I_p2, is adjusted to compensate for “delay to output” as shown in FIG. 4, but differences between Equations 7 and 8 have not been taken into account. Also, FIG. 7 does not appear to have taken into account the varying ratio of
      I_i2    I_p2    .Hence the maximum energy is not constant over the entire range of bulk voltage. For example, as shown by a curve 1300, the maximum energy decreases significantly with decreasing bulk voltage in CCM mode, even though the maximum energy appears substantially constant in the DCM mode.
FIGS. 8 and 9 are simplified conventional timing diagrams for a switch-mode converter in the DCM mode and in the CCM mode respectively. In FIG. 8, curves 810, 820, 830, and 840 represent the timing diagrams in the DCM mode for a secondary current (e.g., is) that flows through a secondary winding, a primary current (e.g., ip) that flows through a primary winding, a drive signal (e.g., Gate) that is used to drive a switch, and a demagnetization signal (e.g., Demag) respectively. In FIG. 9, curves 910, 920, 930, and 940 represent the timing diagrams in the CCM mode for the secondary current (e.g., is) that flows through the secondary winding, the primary current (e.g., ip) that flows through the primary winding, the drive signal (e.g., Gate) that is used to drive the switch, and the demagnetization signal (e.g., Demag) respectively. The secondary current (e.g., is) is equal to an output current of the switch-mode converter according to some embodiments.
In order to improve consistency of maximum energy in the CCM mode and the DCM mode, the compensation slope for the current threshold or the corresponding voltage threshold can be made different in different modes. Specifically, as shown in Equations 7 and 8, the compensation slope in the CCM mode is greater than the compensation slope in the DCM mode in magnitude. But the maximum energy of the power converter can also be affected by other characteristics of the system, such as inductance of the primary winding.
Hence it is highly desirable to improve techniques for over-current protection and over-power protection.